Computer Hardware Fundamentals
Computer hardware is the physical equipment inside a computer case: the motherboard, processor, memory modules, storage drives, power supply, and the buses and connectors that link them into one working platform. An operating system and its firmware run on top of this equipment, and IT staff assemble, upgrade, and diagnose it directly.
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Intro
Computer Hardware Fundamentals
A computer is a set of physical components that plug into a common backbone and cooperate to fetch, move, and store data. The motherboard is that backbone: a printed circuit board that carries the processor socket, memory slots, storage connectors, expansion slots, and the wiring, or buses, that move data between them. Every other component is either mounted directly on the motherboard or connects to it through a defined interface. Software, including the operating system, only runs once this physical platform has powered on, tested itself, and handed control to a boot loader.
This course covers desktop and server-class hardware: the parts a technician selects, assembles, upgrades, and diagnoses. It does not cover instruction sets or processor microarchitecture, which the companion CPU Architecture and Computer Architecture Fundamentals courses address, or the deeper protocol detail in PCI Express, Storage Hardware, Memory Hierarchy, and Firmware, BIOS, and UEFI.
The motherboard and the chipset
The motherboard routes electrical signals between components using buses: sets of parallel or serial wires that carry address, data, and control signals. A memory bus connects the processor directly to RAM. An expansion bus, PCI Express, connects the processor to add-in cards. A separate, lower-speed set of buses connects storage controllers, USB controllers, and onboard audio and network circuits.
On most desktop and laptop platforms, a single companion chip, the chipset, provides the second group of connections. Intel calls this chip the Platform Controller Hub (PCH); AMD's equivalent is generally referred to as its own platform chipset. The PCH connects to the processor over a dedicated link and, in turn, exposes SATA ports for storage, additional PCI Express lanes, USB controllers, low-speed management buses such as SPI and I2C, integrated audio, and system management functions such as the real-time clock and thermal sensors. Older platforms split this work across two chips: a northbridge, wired directly to the processor, that handled the fastest connections to memory and graphics, and a southbridge that handled slower peripherals. Modern processors absorb the northbridge's memory controller and primary PCI Express lanes directly into the CPU package, leaving the PCH to manage the remaining, slower I/O.
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Sources
- https://openstax.org/books/introduction-computer-science/pages/5-1-computer-systems-organization
Supports
- A computer's CPU fetches, decodes, and executes instructions
- RAM is faster than storage and holds instructions/data a program needs now
- Components connect through a bus, a collection of wires that transfers data
- A memory controller facilitates CPU-memory communication
- Cache memory is faster than RAM and sits closer to the processor
- Expansion slots let a system add devices such as alternative displays
- A USB controller manages connected devices
- https://www.corsair.com/us/en/explorer/diy-builder/cases/atx-vs-microatx-vs-mini-itx-whats-the-difference/
Supports
- ATX boards measure 305 x 244 mm
- microATX boards measure up to 244 x 244 mm
- Mini-ITX boards measure 170 x 170 mm
- ATX supports four RAM slots and multiple PCIe x16 slots
- microATX supports up to two PCIe x16 slots and has fewer USB/SATA/M.2 ports than ATX
- Mini-ITX supports two RAM slots and one PCIe x16 slot, and constrains cooling and component choices
- A case built for a given form factor accepts that board or a smaller one
- https://uefi.org/specs/UEFI/2.11/02_Overview.html
Supports
- UEFI is a specification defining how firmware and an operating system interface
- UEFI defines boot and runtime services used to boot a system and pass control to the OS
- https://uefi.org/specs/UEFI/2.11/03_Boot_Manager.html
Supports
- The UEFI boot manager loads UEFI applications, including OS boot loaders, based on an order defined by global NVRAM variables
- The boot manager is a firmware policy engine configured through NVRAM variables
- https://docs.oracle.com/en/operating-systems/oracle-linux/8/boot/boot-AboutUEFIBasedBooting.html
Supports
- POST detects and verifies core hardware such as CPU and memory before UEFI firmware is initialized
- UEFI firmware detects peripheral components such as storage and network devices after POST
- The boot loader is located on a GPT EFI System Partition and control passes to it after firmware initialization
- A silent POST failure (fans on, no video, no boot activity) points to a stage before the OS ever loads
- https://www.kernel.org/doc/html/latest/PCI/index.html
Supports
- PCI and PCI Express are treated as the system's device-connection subsystem, discoverable in software regardless of physical slot
- PCIe lane/slot allocation and negotiated link width are properties the operating system can query
- https://www.jedec.org/standards-documents/docs/jesd79-5d
Supports
- JEDEC defines DDR5 SDRAM's features, functionality, AC/DC characteristics, and module requirements
- DDR5 operates at 1.1V versus DDR4's 1.2V and roughly doubles DDR4's end-of-life bandwidth
- A DRAM generation's electrical and mechanical requirements are generation-specific, so modules are not interchangeable across generations
- https://www.jedec.org/news/pressreleases/jedec-publishes-new-ddr5-standard-advancing-next-generation-high-performance
Supports
- JEDEC published the DDR5 SDRAM standard (JESD79-5) in July 2020
- https://sata-io.org/serial-ata-documentation-overview
Supports
- SATA is a point-to-point interface supporting one device per controller connection
- SATA Revision 1 reached 1.5 Gbps, Revision 2 reached 3 Gbps, Revision 3 reached 6 Gbps
- SATA uses a data cable with seven conductors and 8 mm wafer connectors
- https://sata-io.org/developers/sata-ecosystem/sata-m2-card
Supports
- M.2 is a connector/form-factor specification (formerly NGFF) co-developed by PCI-SIG and SATA-IO
- An M.2 connector can carry PCI Express, SATA, or USB signaling depending on the host and module
- M.2 connector keying notches denote which interfaces a given host/module combination supports
- https://nvmexpress.org/specifications/
Supports
- The NVMe Base Specification defines a protocol for host communication with non-volatile memory over PCIe and other transports
- NVMe supports large numbers of parallel I/O queues and outstanding commands, unlike older single-queue-oriented interfaces
- https://nvmexpress.org/wp-content/uploads/NVM-Express-1_0-Gold.pdf
Supports
- The NVM Express 1.0 specification was published March 1, 2011
- https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/intel-600-series-chipset-family-platform-controller-hub-pch-datasheet-volume/004/introduction/
Supports
- A Platform Controller Hub provides SATA, PCI Express, USB (xHCI/xDCI), audio, Ethernet, and management-bus (eSPI, SPI, I2C, SMBus) interfaces
- The PCH manages I/O subsystems as the desktop platform's central connectivity hub alongside the CPU
- https://edc.intel.com/content/www/xl/es/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1/pci-express-add-in-card-considerations/
Supports
- ATX power supplies deliver multiple DC voltage rails including 12V, 5V, 3.3V, and 5V standby
- Standard PSU connectors include the 24-pin main power connector, 4-pin/8-pin CPU connectors, SATA power connectors, and PCIe auxiliary connectors
- PCIe add-in card power delivery has grown to accommodate higher-power graphics cards via dedicated high-power connectors
- https://www.usb.org/documents
Supports
- USB-IF publishes and maintains the USB specification family (USB 2.0, USB 3.2, USB4) and the USB Type-C/Power Delivery specifications
- USB 3.2 defines multiple transfer-rate tiers (5, 10, and 20 Gbps)
- https://vesa.org/displayport-developer/about-displayport/
Supports
- DisplayPort is a packet-based, extensible protocol for transporting digital video and audio
- DisplayPort is maintained by VESA and supports adapters to legacy VGA, DVI, and HDMI displays
- https://www.clearesult.com/80plus/program-details
Supports
- 80 PLUS certifies power supplies exceeding 80% efficiency at 20%, 50%, and 100% of rated load
- 80 PLUS certification tiers rise from Standard through Bronze, Silver, Gold, Platinum, and Titanium
- https://timeline.intel.com/1993/peripheral-component-interconnect-bus
Supports
- The PCI bus was introduced in November 1993 and standardized how hardware devices connect to computers
- Intel made PCI freely available, enabling rapid adoption by major computer makers
- https://americanhistory.si.edu/collections/object/nmah_1323282
Supports
- The IBM PC 5150 was introduced August 12, 1981, with an Intel 8088 processor
- The IBM PC 5150 used an open architecture with published technical documentation and expansion slots that enabled third-party hardware
- https://www.computerhope.com/jargon/a/atx.htm
Supports
- Intel released the original ATX specification in July 1995
- ATX was the first major change in desktop case, motherboard, and power-supply design in years
- https://ethw.org/Milestones:Universal_Serial_Bus_(USB),_1996
Supports
- The USB 1.0 specification was published January 15, 1996 by a group including Compaq, DEC, IBM, Intel, Microsoft, NEC, and Nortel
- https://0x04.net/~mwk/doc/pci/PCI%20Express%20Base%20Specification%20v1.0%20-%202002.pdf
Supports
- The PCI Express Base Specification Revision 1.0 was published April 29, 2002
- https://storusint.com/pdf/storage_protocols/sata/serialata10a.pdf
Supports
- The Serial ATA 1.0a specification was published January 7, 2003, establishing the first-generation serial storage interface at 1.5 Gbps
- https://itvarnews.techplusmedia.com/2018/07/13/intel-platform-controller-hub/
Supports
- Intel introduced the Platform Controller Hub in 2008, replacing the separate northbridge/southbridge Intel Hub Architecture
- The PCH absorbed remaining southbridge duties plus some northbridge duties such as system clocking, while the memory controller and PCIe lanes moved into the CPU
- https://learn.microsoft.com/en-us/previous-versions/windows/hardware/cert-program/windows-hardware-certification-requirements-for-client-and-server-systems
Supports
- Windows 8 hardware certification required client systems to enable UEFI Secure Boot by default, published in Microsoft's December 2011 certification requirements
