x86-64 Architecture
x86-64 is the 64-bit extension of the x86 instruction-set architecture used by most desktop and server PCs. It defines the instructions, registers, operating modes, memory rules, and protection mechanisms that software and operating systems rely on when they run on an x86-64 processor.
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Don't Panic
Don't Panic — x86-64 Architecture
x86-64 is the rulebook that lets a compiled program and a processor agree on what an instruction means. It is not the blueprint for a particular chip, which is fortunate because a chip blueprint would be a very poor thing to fit into an executable. AMD calls its extension AMD64; Intel calls its compatible version Intel 64. The binary mostly cares that the promised rules line up.
The first useful separation is between the ISA, the instruction-set architecture, and the microarchitecture hiding underneath it. The ISA says that registers exist, instructions have effects, and exceptions occur. The microarchitecture decides how many pipelines, caches, and prediction mechanisms turn that promise into a real processor. Same binary, different machinery, and possibly a very different afternoon spent measuring it.
The second separation is the ABI, the agreement between compiled functions. The ISA provides registers, but the ABI decides which ones carry arguments, which ones survive a call, and how the stack stays aligned. System V and Microsoft x64 make different choices while sharing x86-64 underneath. So “it is x86-64 assembly” is not yet a complete address; it still needs a platform.
Memory also declines to be merely a number. An instruction forms an effective address, then paging translates it through page tables and checks permissions. The address must be canonical for the implementation's configured width. A value can fit in 64 bits and still be rejected before it reaches ordinary memory. The processor is being fussy because the alternative is allowing nonsense to become an exciting kind of bug.
Features arrive as another layer of paperwork. CPUID reports optional facilities, and an operating system may need to enable state before software can use them. A virtual machine can expose only a selected baseline so it can move between compatible hosts. Long mode therefore does not mean every later instruction is safe to execute. It means the door is open; it does not mean every room is furnished.
Read the Introduction for the complete path from instruction bytes to paging and privilege. Use Slides for the layer map and failure clues. Keep the Cheatsheet nearby when registers, addressing, ABI rules, or CPUID checks become suspicious. The Reference tab leads to the manuals that settle arguments with documentation, which is often less dramatic than arguing with a processor and much more effective.
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Sources
- https://docs.amd.com/v/u/en-US/40332_4.09_APM_PUB
Supports
- AMD64 programming model, registers, modes, instructions, memory, paging, protection, and exceptions
- Long mode and compatibility mode
- CPUID feature discovery
- AMD64 specification history used by the timeline
- Quiz answers about ISA, compatibility mode, canonical addresses, and feature detection
- https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
Supports
- Intel 64 architecture, programming environment, instruction reference, and system programming
- Variable-length instruction encoding, REX, exceptions, privilege, paging, TLB behavior, CPUID, and virtualization
- Separation of architectural semantics from model-specific optimization
- Quiz answers about ISA, instruction boundaries, feature detection, and virtual CPU baselines
- https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-architecture
Supports
- AMD64 and Intel 64 as the x64 platform
- Sixteen general-purpose registers and subregister naming
- Zero-extension after 32-bit register writes
- RIP-relative addressing and 64-bit instruction behavior
- Quiz answers about subregisters and addressing
- https://gitlab.com/x86-psABIs/x86-64-ABI
Supports
- System V AMD64 calling convention, stack, data layout, ELF, and relocations
- Argument-register order, red zone, alignment, and register preservation
- Quiz answers comparing platform ABIs
- https://learn.microsoft.com/en-us/cpp/build/x64-software-conventions
Supports
- Microsoft x64 data layout, registers, calling, stack, and unwind rules
- Volatile and nonvolatile register classes
- Quiz answer about ABI-defined register preservation
- https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention
Supports
- RCX, RDX, R8, and R9 argument registers
- Caller-provided shadow space and stack requirements
- Return values and register volatility
- Quiz answer comparing System V and Microsoft conventions
- https://docs.kernel.org/arch/x86/index.html
Supports
- Linux-specific boot, paging, kernel-stack, exception, and x86 behavior
- Reference-path rationale
- https://docs.kernel.org/arch/x86/x86_64/mm.html
Supports
- Four-level and five-level x86-64 virtual-memory layouts
- Implemented address-space limits
- Quiz answer about valid virtual addresses
- https://www.qemu.org/docs/master/system/qemu-cpu-models.html
Supports
- Named x86 CPU models, feature exposure, compatibility, and migration considerations
- Virtual CPU product description and reference rationale
- Quiz answer about migration baselines
- https://sourceware.org/binutils/docs/as/
Supports
- GNU assembler syntax, directives, machine selection, and x86-dependent options
- Reference-path rationale
- https://github.com/sindresorhus/awesome
Supports
- Required starting point for Awesome Links research
- https://github.com/Hack-Labs/awesome-assembler
Supports
- Discovery of NASM, FASM, Capstone, IDA Free, and Radare2
- Classification of assemblers, disassemblers, and debuggers
- https://www.nasm.us/
Supports
- NASM as a portable x86 assembler with platform code generation
- NASM Awesome Links rationale
- https://www.capstone-engine.org/documentation.html
Supports
- Embeddable disassembly API and x86 decoding support
- Capstone Awesome Links rationale
- https://book.rada.re/
Supports
- Binary analysis, disassembly, register and memory inspection, and debugging
- Radare2 Awesome Links rationale
- https://flatassembler.net/
Supports
- FASM x86 assembler and multi-pass assembly model
- FASM Awesome Links rationale
- https://hex-rays.com/ida-free
Supports
- IDA Free interactive disassembly and static binary analysis
- IDA Free Awesome Links rationale
- https://www.intel.com/pressroom/kits/quickrefyr.htm
Supports
- 1978 introduction and historical role of the 8086
- https://www.intel.com/pressroom/kits/quickrefyr.htm
Supports
- 1985 introduction of the Intel 386 processor
- https://www.kernel.org/doc/ols/2001/x86-64.pdf
Supports
- Early Linux x86-64 kernel, toolchain, and ABI work
- 2001 timeline milestone
- https://ir.amd.com/financial-information/sec-filings/content/0001193125-04-037179/d10k.htm
Supports
- April 2003 Opteron introduction
- Opteron support for 32-bit and 64-bit applications
- https://ir.amd.com/financial-information/sec-filings/content/0001193125-03-090748/dposam.htm
Supports
- September 2003 Athlon 64 introduction
- Desktop and mobile placement of AMD64 processors
- https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-05-033162/d10k.htm
Supports
- June 2004 Xeon introduction with Intel Extended Memory 64 Technology
- Support for 32-bit and 64-bit operating systems and applications
- https://news.microsoft.com/source/2005/04/25/microsoft-raises-the-speed-limit-with-the-availability-of-64-bit-editions-of-windows-server-2003-and-windows-xp-professional/
Supports
- General availability date for Windows XP Professional x64 and Windows Server 2003 x64
- Native 64-bit and supported 32-bit application platform
- https://developer.apple.com/library/archive/documentation/Darwin/Conceptual/64bitPorting/intro/intro.html
Supports
- 64-bit application support in Mac OS X 10.5
- 64-bit kernel introduction in Mac OS X 10.6 on supported hardware
- https://www.intel.com/content/www/us/en/products/details/processors/xeon.html
Supports
- Xeon placement in server and workstation x86-64 deployments
- Xeon Landscape entry
- https://www.amd.com/en/products/processors/server/epyc.html
Supports
- EPYC placement in server AMD64 deployments
- EPYC Landscape entry
- https://www.intel.com/content/www/us/en/products/details/processors/core.html
Supports
- Core placement in desktop and mobile Intel 64 deployments
- Intel Core Landscape entry
- https://www.amd.com/en/products/processors/desktops/ryzen.html
Supports
- Ryzen placement in desktop AMD64 deployments
- Ryzen Landscape entry
- https://www.gnu.org/software/binutils/
Supports
- Assembler, linker, and binary inspection toolchain
- GNU Binutils Landscape entry
- https://llvm.org/
Supports
- Compiler infrastructure and x86 target configuration
- LLVM Landscape entry
- https://visualstudio.microsoft.com/
Supports
- Microsoft x64 compiler, debugger, assembler, and linker tooling context
- Visual Studio Landscape entry
- https://sourceware.org/binutils/docs/binutils/objdump.html
Supports
- Disassembly and file-header inspection commands used by the practice reference and exercise
- https://developers.redhat.com/blog/2020/03/13/possible-issues-with-debugging-and-inspecting-compiler-optimized-binaries
Supports
- Field Note: compiler output and debug information are the evidence for optimized binary inspection
- https://developers.redhat.com/articles/2023/06/19/debugging-gdb-create-custom-stack-winders
Supports
- Field Note: nonstandard stack manipulation can defeat ordinary unwinding
- https://www.agner.org/optimize/optimizing_assembly.pdf
Supports
- Field Note: hand-written assembly can forfeit compiler interprocedural optimization
- https://developers.redhat.com/articles/2022/01/10/gdb-developers-gnu-debugger-tutorial-part-2-all-about-debuginfo
Supports
- Field Note: DW_AT_producer exposes compiler and build options
