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PCI Express

PCI Express is a high-speed, point-to-point interconnect that carries data between a computer's processor and devices such as graphics adapters, storage controllers, and network cards. It combines one or more serial lanes into a link whose speed and width are negotiated when the system starts.

itComputer architecture and hardware

Don't Panic: PCI Express

PCI Express, usually called PCIe, is the packet road between a computer's processor and its fast peripherals. Graphics adapters, NVMe storage, network adapters, accelerators, and FPGA cards use it. Before PCIe, PCI was a shared parallel bus. PCIe replaced that communal table with separate conversations, which is tidier until several conversations need the same exit.

The shape to keep in mind is a tree of point-to-point links. A root complex connects processor and memory to the hierarchy. A root port begins one link. An endpoint is the device at the far side. A switch grows more downstream links, but it does not manufacture extra upstream capacity. That last detail explains why a topology can look generously populated while its busiest path behaves like a narrow doorway at lunch.

Each link is made from lanes. A lane has one differential pair to transmit and another to receive, so it is full duplex. Width counts active lanes. A generation sets the rate per lane. They are separate knobs. An x16 connector can have fewer electrical lanes, and a newer card can run at an older generation. The advertised maximum is a possibility, not a sworn affidavit.

Before useful software work begins, the neighboring ports train the link. They agree on a usable width and generation. Firmware or the operating system then finds the device in configuration space, assigns its BAR, an address window for registers or device memory, and binds a driver. Bulk work usually uses DMA, where the endpoint moves data to or from host memory. The driver sets up buffers; PCIe carries the packets; the device protocol gives those packets a job description.

Inside every port, the transaction layer creates reads, writes, completions, configuration requests, and messages. The data-link layer checks delivery on that one hop. The physical layer trains and signals it. This is why an error can be very local. A switch forwards transactions onward, but acknowledgment and replay do not tour the whole tree like anxious tourists.

The surprise is that bandwidth is not one number. Generation times width gives raw link capacity, while encoding, packet overhead, flow control, retries, transaction latency, topology, and software decide what becomes useful work. A memory read waits for a completion with data. A posted memory write does not. Two workloads on the same nominal link can therefore feel as though they were given different roads.

Read the Intro when you need the complete architecture and failure model. Use the Slides to keep the tree, layers, and data path in one picture. The Cheatsheet is for comparing capability with negotiated state while diagnosing a real link. Field Notes covers the operational traps that begin before a driver has anything to complain about. The Quiz checks whether the terminology has stopped behaving like an acronym convention.

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