PCI Express
PCI Express is a high-speed, point-to-point interconnect that carries data between a computer's processor and devices such as graphics adapters, storage controllers, and network cards. It combines one or more serial lanes into a link whose speed and width are negotiated when the system starts.
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Intro
PCI Express
What PCI Express is
PCI Express, usually shortened to PCIe, is a packet-based serial interconnect for moving data between a host processor and peripheral devices. Graphics adapters, NVMe storage, network adapters, accelerators, and FPGA cards commonly use it. PCIe preserves the software discovery model of earlier PCI while replacing the shared parallel bus with point-to-point links.
A PCIe link connects exactly two ports. A root port connects the processor's root complex to the fabric. An endpoint terminates the fabric at a device. A switch adds downstream ports when one root port must reach several endpoints. Each link is full duplex, so traffic can move in both directions at the same time.
The fabric and its links
The root complex is the host-side bridge between processors and memory on one side and the PCIe hierarchy on the other. Firmware and the operating system enumerate the hierarchy, assign address ranges, and bind each discovered function to a driver. A direct-attached endpoint forms the smallest hierarchy:
processor and memory
|
root complex
|
root port
|
PCIe link
|
endpoint
A switch keeps the same tree-shaped software view while routing packets across several links:
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Sources
- https://pcisig.com/what-pci-express-pcie-architecture
Supports
- PCIe as a scalable interconnect architecture
- Lane aggregation and supported link-width concept
- Hot-plug, power-management, and quality-of-service capabilities
- Novice definition and point-to-point fabric orientation
- https://pcisig.com/specification-overview/pci-express-base
Supports
- Base architecture scope and programming-interface purpose
- Approval dates for PCIe base specification revisions 1.1 through 7.0
- Resizable BAR engineering-change publication date
- Related configuration, link, transaction, physical, and retimer test specifications
- Timeline generation milestones
- https://pcisig.com/sites/default/files/files/01_01_PCI_Express_Basics_%26_Background_FROZEN.pdf
Supports
- Transaction, data-link, and physical-layer model
- TLP and DLLP roles
- ACK, NAK, replay, and credit-based flow control
- Memory read, memory write, completion, configuration, and message transactions
- https://www.intel.com/content/dam/doc/white-paper/pci-express-initiatives-and-technology-article.pdf
Supports
- Point-to-point serial architecture and three functional layers
- Protocol reliability across the transaction, data-link, and physical layers
- Packet and encoding overhead in throughput analysis
- Host, switch, and endpoint design context
- https://pcisig.com/blog/pushing-limits-understanding-lane-margining-pcie%C2%AE
Supports
- PCIe 4.0 at 16 GT/s per lane
- Backward compatibility across generations
- Signal margin and channel loss as higher-rate implementation concerns
- Diagnosis of downtrained speed and width
- https://pcisig.com/sites/default/files/files/02_01_Troubleshooting_PCI_Express_Link_Training_and_Protocol_Issues_FROZEN.pdf
Supports
- LTSSM and physical-layer troubleshooting context
- Separation of transaction, data-link, and physical-layer fault domains
- Link-training evidence used in the quiz and cheatsheet
- https://pcisig.com/pci-express-6.0-specification
Supports
- 64.0 GT/s raw rate and backward compatibility
- PAM4 signaling, FLIT-based encoding, FEC, and strong CRC
- Up to 256 GB/s bidirectional bandwidth for x16
- PCIe 6.0 timeline milestone and quiz answer
- https://pcisig.com/faq?field_category_value%5B%5D=pci_express_6.0&keys=PAM4
Supports
- PAM4 representing two bits with four signal levels
- Fixed 256-byte FLIT structure and reason for fixed-size transport
- FEC, CRC, NAK, and replay response to the PAM4 error environment
- https://pcisig.com/specifications/pcie-70-specification-version-03-now-available-members
Supports
- PCIe 7.0 release on 2025-06-11
- 128.0 GT/s raw rate and doubled PCIe 6.x rate
- Up to 512 GB/s bidirectional bandwidth for x16
- https://pcisig.com/specification-overview/pci-express-m2
Supports
- M.2 as a family of smaller mobile-adapter form factors
- M.2 Specification Revision 1.0 approval on 2013-11-01
- Timeline M.2 milestone
- https://pcisig.com/specification-overview/pci-express-cem
Supports
- CEM as a qualified add-in-card implementation of the base architecture
- Separation of connector and card rules from base protocol behavior
- https://pcisig.com/sites/default/files/The%20Evolution%20of%20the%20PCI%20Express%20Specification%20On%20its%20Sixth%20Generation%20Third%20Decade%20and%20Still%20Going%20Strong_Contributed%20Article.pdf
Supports
- Generation data-rate progression and encoding changes
- Backward-compatible evolution through PCIe 6.0
- Timeline descriptions for PCIe 3.0 and later generations
- https://www.kernel.org/doc/html/latest/PCI/index.html
Supports
- PCI device discovery, configuration space, resources, and drivers
- PCIe port services, error recovery, SR-IOV, MSI, sysfs, and endpoint framework
- Reference-path rationale
- https://www.kernel.org/doc/html/latest/PCI/pci.html
Supports
- Device enablement, MMIO and I/O resource requests, DMA setup, and interrupt registration
- Driver initialization and shutdown responsibilities
- BAR and resource-allocation quiz answer
- https://www.kernel.org/doc/html/latest/PCI/pciebus-howto.html
Supports
- Root Port, Switch Upstream Port, and Switch Downstream Port roles
- PCIe port services including hot-plug, PME, AER, and virtual channels
- Switch topology and service-driver context
- https://docs.kernel.org/PCI/pcieaer-howto.html
Supports
- Baseline and Advanced Error Reporting capabilities
- Correctable and uncorrectable log behavior
- AER attachment to Root Ports and Root Complex Event Collectors
- Firmware grant of AER control through ACPI before Linux handles events
- https://docs.kernel.org/PCI/pci-iov-howto.html
Supports
- SR-IOV as an extended capability exposing physical and virtual functions
- Per-function configuration space, memory space, drivers, and dynamic VF control
- Virtualization section in the intro
- https://github.com/sindresorhus/awesome
Supports
- Discovery path into the curated open-source hardware list
- https://github.com/aolofsson/awesome-opensource-hardware
Supports
- Discovery of cocotbext-pcie, pcievhost, LitePCIe, and verilog-pcie
- Classification of the selected projects as PCIe verification or connectivity resources
- https://github.com/alexforencich/cocotbext-pcie
Supports
- Simulated root complex, switches, devices, functions, configuration spaces, and BAR allocation
- Memory, DMA, message-signaled interrupt, and multi-device testbench rationale
- https://github.com/enjoy-digital/litepcie
Supports
- Configurable FPGA PCIe core, PHY integrations, DMA, software driver, and generated RTL
- https://github.com/alexforencich/verilog-pcie
Supports
- Verilog PCIe components, FPGA integrations, DMA components, and cocotbext-pcie testbenches
- https://github.com/wyvernSemi/pcievhost
Supports
- Virtual root-complex model for HDL simulation
- Generated physical, data-link, and transaction-layer traffic
- TLP, DLLP, ACK, NAK, flow-control, and training-sequence controls
- https://www.synopsys.com/designware-ip/interface-ip/pci-express/pci-express-controllers.html
Supports
- Configurable endpoint, root-port, dual-mode, and switch-port controller roles
- Synopsys Landscape placement
- https://www.cadence.com/en_US/home/tools/silicon-solutions/design-ip/pcie-and-compute-express-link/phy-for-pcie-and-cxl/phy-for-pcie-6-and-cxl.html
Supports
- PCIe 6.0 PAM4 SerDes PHY and controller pairing
- Cadence Landscape placement
- https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/7_series_pci_express_block.html
Supports
- FPGA integrated PCIe block configuration and added endpoint logic
- Vivado support and proprietary license classification
- https://www.intel.com/content/www/us/en/ark/products/series/237646/interface-protocols-pci-express.html
Supports
- Intel FPGA scalable switch and SR-IOV PCIe IP offerings
- Intel Landscape placement
- https://www.microchip.com/en-us/products/interface-and-connectivity/pcie/pcie-switches
Supports
- Fan-out, multi-host, hot-plug, error containment, and diagnostics roles
- Microchip Landscape placement
- https://www.broadcom.com/products/pcie-switches-retimers/pcie-switches
Supports
- Broadcom PCIe switching portfolio and configurable switch role
- Broadcom Landscape placement
- https://www.asteralabs.com/products/pcie-cxl-smart-dsp-retimers/
Supports
- Signal-integrity reach extension and link telemetry
- Retimer role in the intro, quiz, cheatsheet, and Landscape
- https://www.teledynelecroy.com/protocolanalyzer/pci-express/
Supports
- PCIe traffic capture, decoding, interposers, compliance, exerciser, and error-injection roles
- Summit Landscape placement
- https://www.keysight.com/gn/en/products/digital-protocol-analyzers/pcie-protocol-exercisers.html
Supports
- Root-complex and endpoint emulation, link-training control, traffic generation, and error injection
- Keysight Landscape placement
- https://resources.sw.siemens.com/en-US/fact-sheet-verification-ip-for-pcie/
Supports
- Verification support for root complexes, endpoints, switches, and retimers
- Protocol checkers, transaction logging, coverage, and performance statistics
- Questa Landscape placement