Memory Hierarchy
Memory hierarchy arranges registers, caches, main memory, and storage in layers with different speed, capacity, and cost. It keeps frequently used data near the processor while larger, slower layers retain the rest.
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Don't Panic
Don't Panic — Memory Hierarchy
Every processor faces the same annoying fact: no single kind of memory is fast, huge, cheap, and permanent at once. Something has to give. The memory hierarchy is the compromise computer designers settled on: stack up several kinds of storage, keep the smallest and fastest closest to the processor, and let the big slow stuff sit farther away holding everything else.
Before you picture a tidy pyramid, know that the pyramid is a teaching prop, not a blueprint. The real path runs from registers through one or more caches, into main memory, and sometimes onward to a disk or SSD standing in for memory it can't otherwise hold. Nothing forces a request to visit every layer. Most don't, and that's the entire point.
The reason this works at all is locality: programs tend to reuse the same data soon (temporal) or touch data sitting near what they just touched (spatial). A hierarchy is a bet that your program has some, and most programs do.
When a requested value is already sitting in the nearby layer, that's a hit. When it isn't, the search continues downward, and that's a miss, the same word reused, confusingly, for three different events with three different costs: a cache miss, a TLB miss (translation, not data), and a page fault (the operating system getting involved). Keeping those apart is worth the effort; conflating them is how performance debugging goes sideways.
Here's the bit that trips people up even after they've drawn the pyramid correctly: two threads can write to completely unrelated variables and still slow each other down, because the hardware doesn't move data byte by byte — it moves whole cache lines. If your two "independent" counters happen to land on the same line, the cores fight over ownership of it constantly, and the resulting slowdown looks exactly like a lock problem to anyone watching a profiler. It isn't one. It's a layout problem wearing a lock problem's clothes.
None of this is exotic wizardry reserved for kernel engineers. It's the layer beneath every "why is this slower than it should be" investigation you'll ever run, whether you're tuning a database, a game engine, or a script that felt fine until the input got large.
Where to go next: the Cheatsheet has the vocabulary and the AMAT formula in dense reference form, the Slides give you the visual map if prose isn't landing, and Field Notes is where the judgment lives, what teams get wrong about scaling versus locality, and what a stalled processor's utilization graph actually tells you. And if you want to check whether any of this stuck, the Quiz is right there waiting.
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Sources
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c14/c14s1/
Supports
- Layered use of registers, multilevel SRAM caches, DRAM, and nonvolatile storage
- Locality, cache hits, cache misses, fills, line organization, and management boundaries
- Cache address decomposition, associativity, replacement, and write-policy concepts
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c16/c16s1/
Supports
- Main memory and secondary storage as hierarchy levels
- Virtual addresses, physical addresses, MMU translation, pages, and software-managed misses
- Large blocks, high associativity, and write-back behavior in virtual memory
- https://notes.cs61c.org/content/caches-intro/memory-hierarchy/
Supports
- Memory hierarchy order and the latency, capacity, and cost tradeoff
- Copies across hierarchy levels and hardware or software management roles
- Multilevel cache request flow
- https://notes.cs61c.org/content/caches-intro/amat/
Supports
- Definitions of hit time, miss rate, and miss penalty
- Single-level and recursive multilevel AMAT formulas
- Local lower-level miss rate interpretation
- https://notes.cs61c.org/content/caches-ii/set-associative/
Supports
- Direct-mapped, set-associative, and fully associative placement choices
- Address tag, index, offset, replacement scope, and conflict tradeoffs
- Replacement policies and compatibility with write policies
- https://notes.cs61c.org/content/caches-ii/fully-associative/
Supports
- Write-through and write-back behavior
- Dirty bits and eviction of modified lines
- Cache metadata and line-size tradeoffs
- https://notes.cs61c.org/content/parallel-tlp/cache-coherency/
Supports
- Compulsory, capacity, and conflict miss classification
- Coherence needs when several processors cache shared data
- https://notes.cs61c.org/content/vm/
Supports
- Virtual and physical address spaces, pages, page tables, and isolation
- Main memory as a cache for storage-backed data
- Distinction between cache hierarchy and virtual-memory mechanisms
- https://notes.cs61c.org/content/vm/memory-hierarchy-full/
Supports
- TLB and page-table translation integrated with cache lookup
- Full request path from virtual address to physical memory
- https://www.intel.com/content/www/us/en/developer/articles/technical/intel64-and-ia32-architectures-optimization.html
Supports
- Implementation-specific cache, memory, prefetch, and performance guidance
- Need to consult processor-specific documentation for tuning
- Product documentation path for Intel VTune-oriented memory analysis
- https://docs.kernel.org/core-api/real-time/hardware.html
Supports
- Caches and main memory as shared resources
- Cache contention, cache misses, cache-to-cache issues, and Linux perf measurement
- Workload interference through memory and buses
- https://docs.kernel.org/mm/numa.html
Supports
- NUMA nodes, local and remote memory, interconnect distance, latency, and bandwidth
- Local allocation, scheduling, affinity, and page-placement considerations
- Hardware cache coherence in ccNUMA systems
- https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/extended-system-coherency---part-1---cache-coherency-fundamentals
Supports
- Stale cached copies, line cleaning, invalidation, and hardware or software coherence
- Sharing data between processors and other bus masters
- Difference between cache visibility work and application synchronization
- https://developer.arm.com/-/media/Files/downloads/research/Research%20Enablement%20Kits/System%20modeling%20using%20gem5/gem5_rsk.pdf?revision=d4f12030-bdca-4db5-bfa3-b36e15dc49e7
Supports
- TLB as a cache of recent page translations
- Translation entries containing addresses, attributes, and permissions
- https://docs.riscv.org/reference/isa/unpriv/mm-eplan.html
Supports
- Separation of architectural memory ordering from a specific cache hierarchy
- Coherent and non-coherent implementations under a software-visible memory model
- https://www.intel.com/content/www/us/en/docs/vtune-profiler/user-guide/2023-0/memory-access-analysis.html
Supports
- Intel VTune memory analysis for cache misses, NUMA, bandwidth, and memory objects
- L1, L2, L3, DRAM, and remote-access performance metrics
- Intel VTune placement in the memory-analysis tool landscape
- https://docs.amd.com/r/en-US/57368-uProf-user-guide/Cache-Analysis-Using-GUI
Supports
- AMD uProf cache-line sampling and cache-analysis reports
- AMD uProf placement in the memory-analysis tool landscape
- https://valgrind.org/docs/manual/manual-intro.html
Supports
- Cachegrind as a cache and branch-prediction profiler
- Valgrind and Cachegrind placement in the software-simulation tool landscape
- https://www.gem5.org/documentation/
Supports
- gem5 cache, coherence, interconnect, and memory-system models
- gem5 as a learner destination and architecture research simulator
- https://champsim.github.io/ChampSim/master/
Supports
- ChampSim trace-driven modeling and configurable cache hierarchy
- Cache replacement, prefetcher, associativity, and memory experiments
- https://github.com/CMU-SAFARI/ramulator2
Supports
- Ramulator as a configurable cycle-accurate DRAM simulator
- DRAM standards, controller configuration, and trace-based experiments
- https://openram.org/
Supports
- OpenRAM generation of SRAM layout, netlists, timing, power, and physical-design views
- SRAM compiler role behind cache-array implementation
- https://github.com/aolofsson/awesome-opensource-hardware/blob/main/README.md
Supports
- Discovery of gem5, ChampSim, Ramulator 2.0, and OpenRAM as relevant ecosystem projects
- Curated hardware-tool and memory-project context for Awesome Links
- https://www.ias.edu/library/ecp
Supports
- The 1946 Preliminary Discussion report and its explicit memory-hierarchy framing
- Date and institutional provenance for the early hierarchy milestone
- https://www.computerhistory.org/timeline/memory-storage/
Supports
- Whirlwind core memory in 1953
- Intel 1103 DRAM adoption in 1970 and decline of magnetic core memory
- Institutional history of memory and storage technologies
- https://www.cs.manchester.ac.uk/about/history-and-heritage/
Supports
- Atlas inauguration in 1962
- Atlas as the first computer to use virtual memory
- https://www.ibm.com/history/dram
Supports
- Robert Dennard's 1966 DRAM concept and 1968 patent
- DRAM use of a transistor and capacitor with repeated refresh
- Commercial adoption of semiconductor DRAM around 1970
- https://sigops.org/s/conferences/sosp/2015/history/abstracts.html
Supports
- Atlas as a pioneer of transparent software-managed hierarchy
- IBM System 360 Model 85 as an early hardware cache demonstration in 1968
- https://libraopen.library.virginia.edu/server/api/core/bitstreams/9a576fcb-5a03-4557-a055-3539d7e9c283/content
Supports
- Wulf and McKee's 1995 publication of the memory-wall argument
- Widening processor and memory performance gap as an architecture concern
- https://computeexpresslink.org/blog/introduction-to-compute-express-link-cxl-the-cpu-to-device-interconnect-breakthrough-2313/
Supports
- CXL technology and Specification 1.0 unveiling in March 2019
- Coherent processor-to-device memory access as a newer hierarchy path
- https://www.usenix.org/system/files/conference/hotos15/hotos15-paper-mcsherry.pdf
Supports
- The COST metric and its finding that many published scalable, data-parallel systems needed hundreds of cores to outperform a single competent thread
- Locality-respecting single-threaded implementations as a baseline scalable systems often fail to beat
- https://mechanical-sympathy.blogspot.com/2011/07/false-sharing.html
Supports
- False sharing: independent variables on the same cache line causing cross-core cache-coherence traffic
- Cache-line padding as the fix for false sharing, distinct from lock contention
- https://rhaas.blogspot.com/2014/04/subtly-bad-things-linux-may-be-doing-to.html
Supports
- Strict local NUMA memory allocation causing the kernel to evict hot local pages in preference to cold remote pages under memory pressure
- NUMA-related swapping and reclaim behavior affecting database workloads with large shared memory
- https://www.brendangregg.com/blog/2017-05-09/cpu-utilization-is-wrong.html
Supports
- Instructions-per-cycle as the metric distinguishing memory-stalled from instruction-bound CPU utilization
- IPC below roughly 1.0 as a signal of memory-bound stalling on a four-wide processor
