GPU Architecture
A graphics processing unit, or GPU, is a processor built to run many similar operations in parallel. Its architecture combines groups of execution lanes, fast on-chip memory, caches, and specialized graphics or matrix hardware to favor throughput over fast completion of one instruction stream.
itComputer architecture and hardware | OpenSkills.info
Course pathWalk it in order
Look it upDip in anytime
Go furtherLeaves this page
Intro
GPU Architecture
A graphics processing unit, or GPU, is a throughput processor. It keeps many arithmetic operations in flight so the chip can process large collections of pixels, vertices, matrix elements, particles, or other independent data. A central processing unit, or CPU, usually devotes more hardware to reducing the delay of a few instruction streams. A GPU devotes more hardware to parallel execution and accepts that one item may wait while many other items make progress.
That distinction describes a design priority, not a rule that GPUs are always faster. A workload needs enough parallel work, suitable memory access, and enough computation to repay data movement and launch overhead. Serial control flow, small jobs, irregular pointer chasing, and frequent host-device transfers can leave a GPU underused.
The execution hierarchy
GPU software describes a large set of lightweight work items. CUDA calls them threads. OpenCL and related models use work-items. Hardware collects neighboring work items into an execution group that shares an instruction stream. NVIDIA calls that group a warp; AMD calls it a wavefront. The exact width is architecture-specific, so portable software should obtain it from the programming model or device rather than assume one vendor's width.
A kernel is a function launched across many work items. Software groups the work items into blocks or work-groups. A GPU schedules each block onto a compute unit, such as an NVIDIA streaming multiprocessor, an AMD compute unit, or an Intel Xe-core. Work items in one block can cooperate through fast local storage and block-scoped synchronization. Separate blocks must remain independently schedulable unless a programming model supplies a wider coordination mechanism.
The hierarchy is therefore:
application on host
↓ submits work
kernel grid or dispatch
↓ divided into
blocks or work-groups
↓ divided into
warps, wavefronts, or subgroups
↓ issue across
execution lanes and specialized units
This arrangement lets the same architecture scale. A larger GPU runs more blocks at once; a smaller GPU runs the same blocks in more waves. Correct code does not depend on which block starts first.
What happens inside a compute unit
Continue the course
This section is part of the paid course.
See pricing to subscribe, or log in if you already have access.
Where this skill leads
Relevant careers
See how this topic contributes to broader role-level skill maps.
Sources
- https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html
Supports
- Kernel, grid, block, thread, warp, and SIMT execution hierarchy
- Thread-block scheduling and block independence
- CUDA memory hierarchy and synchronization scope
- Warp divergence and lane grouping
- https://docs.nvidia.com/cuda/archive/12.5.0/cuda-c-programming-guide/index.html
Supports
- Streaming multiprocessor scheduling and hardware multithreading
- Register and shared-memory limits on residency
- Occupancy, warp scheduling, divergence, and independent thread scheduling
- Host and device memory spaces
- https://docs.nvidia.com/cuda/archive/12.8.0/cuda-c-best-practices-guide/
Supports
- GPU throughput orientation and CPU comparison
- Memory coalescing, data locality, divergence, and transfer guidance
- Memory-bound performance and workload suitability
- https://rocm.docs.amd.com/en/latest/reference/glossary/device-hardware.html
Supports
- AMD compute-unit, wavefront, work-group, and local-data-share vocabulary
- Shared instruction stream within a wavefront
- https://rocm.docs.amd.com/en/latest/reference/gpu-arch-specs.html
Supports
- Architecture-specific wavefront sizes
- Compute-unit, register, local-storage, and cache variation across AMD GPUs
- https://rocm.docs.amd.com/projects/rocprofiler-compute/en/docs-6.3.0/conceptual/compute-unit.html
Supports
- Scheduler, scalar unit, vector memory unit, and execution resources in an AMD compute unit
- https://www.amd.com/content/dam/amd/en/documents/instinct-business-docs/white-papers/amd-cdna-white-paper.pdf
Supports
- CDNA compute-unit organization and matrix cores
- Data-center emphasis on HPC and machine-learning compute
- https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2025-2/intel-xe-gpu-architecture.html
Supports
- Intel vector engines, Xe-cores, matrix engines, registers, caches, and shared local memory
- Multi-stack GPU organization
- Architecture and product variation
- https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2024-2/execution-model-overview.html
Supports
- Host, command queue, kernel, compute-device, and vector-engine flow
- GPU compute engines, caches, shared local memory, and high-bandwidth memory
- https://www.intel.com/content/www/us/en/docs/oneapi/programming-guide/2024-2/gpu-offload-flow.html
Supports
- Work-item, subgroup, work-group, compute-unit, and global-range mapping
- https://registry.khronos.org/vulkan/specs/latest/html/vkspec.html
Supports
- Host and device environment
- Asynchronous queues, dependencies, graphics, compute, transfer, and video functionality
- Pipeline, shader, memory, and synchronization concepts
- https://docs.nvidia.com/nsight-compute/NsightCompute/index.html
Supports
- Kernel profiling, performance metrics, report comparison, and analysis workflow
- Occupancy, memory, instruction, and throughput evidence
- https://rocm.docs.amd.com/en/latest/components/profilers-and-debuggers.html
Supports
- AMD kernel counters, system tracing, debugging, and wavefront fault tools
- https://images.nvidia.com/aem-dam/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf
Supports
- Programmable shader resources with tensor, ray-tracing, texture, and graphics units
- Fixed-function and programmable graphics acceleration
- https://developer.apple.com/metal/
Supports
- Integrated Apple GPU graphics and compute programming
- GPU profiling, debugging, and machine-learning integration
- https://github.com/coderonion/awesome-cuda-and-hpc
Supports
- Discovery of CUDA Python, CuPy, CUDA.jl, HIP, and NVBench ecosystem projects
- https://nvidia.github.io/cuda-python/latest/
Supports
- Pythonic CUDA core access and low-level CUDA C API bindings
- https://docs.cupy.dev/en/stable/
Supports
- GPU array operations, custom kernels, memory management, and performance guidance
- https://cuda.juliagpu.org/stable/
Supports
- Julia GPU arrays, hand-written kernels, and low-level CUDA APIs
- https://rocm.docs.amd.com/projects/HIP/en/docs-6.3.1/programming_guide.html
Supports
- Portable C++ GPU kernels and architecture-aware parallelism
- https://github.com/NVIDIA/nvbench
Supports
- CUDA kernel benchmarking, parameter sweeps, timing, and memory-throughput reporting
- https://www.nvidia.com/content/timeline/time_99.html
Supports
- August 1999 GeForce 256 launch and GPU naming milestone
- https://www.nvidia.com/content/timeline/time_01.html
Supports
- February 2001 GeForce3 programmable GPU launch
- https://docs.nvidia.com/cuda/archive/13.1.0/cuda-programming-guide/01-introduction/introduction.html
Supports
- Progression from fixed-function graphics to programmable stages
- 2006 introduction of CUDA for general computational workloads
- https://www.khronos.org/news/permalink/opencl_1.0_released
Supports
- December 2008 ratification and release of OpenCL 1.0
- Cross-platform parallel programming across CPUs, GPUs, and other processors
- https://www.nvidia.com/en-us/drivers/pg-57689/
Supports
- September 2009 announcement of the Fermi CUDA GPU architecture
- https://ir.amd.com/news-events/press-releases/detail/201/amd-launches-worlds-fastest-single-gpu-graphics-card----the-amd-radeontm-hd-7970
Supports
- December 2011 launch of Radeon HD 7970 with Graphics Core Next architecture
- Unified emphasis on graphics and compute capability
- https://www.khronos.org/news/press/khronos-releases-vulkan-1-0-specification
Supports
- February 2016 Vulkan 1.0 release
- Explicit cross-platform graphics and compute control
- https://nvidianews.nvidia.com/news/nvidia-launches-revolutionary-volta-gpu-platform-fueling-next-era-of-ai-and-high-performance-computing
Supports
- May 2017 Volta and Tesla V100 launch
- Introduction of Tensor Cores in a GPU architecture
- https://developer.nvidia.com/blog/?p=11872
Supports
- September 2018 Turing architecture details
- Integration of ray-tracing and tensor hardware with shader resources
- https://instinct.docs.amd.com/projects/system-acceptance/en/latest/gpus/mi100.html
Supports
- First-generation CDNA architecture in AMD Instinct MI100
- Compute-focused GPU for HPC and accelerated computing
- https://www.amd.com/en/newsroom/press-releases/2021-11-8-new-amd-instinct-mi200-series-accelerators-bring-.html
Supports
- November 2021 AMD Instinct MI200 launch
- Multi-die GPU packaging and CDNA 2 matrix acceleration
- https://nvidianews.nvidia.com/news/nvidia-announces-hopper-architecture-the-next-generation-of-accelerated-computing
Supports
- March 2022 Hopper and H100 announcement
- Transformer Engine, newer Tensor Cores, and expanded GPU interconnect
- https://www.nvidia.com/en-us/data-center/
Supports
- NVIDIA data-center GPU platform for AI and accelerated computing
- https://www.amd.com/en/products/accelerators/instinct.html
Supports
- AMD Instinct GPU portfolio for AI and HPC
- https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu.html
Supports
- Intel data-center GPU portfolio for media, AI, and HPC
- https://www.nvidia.com/en-us/geforce/graphics-cards/
Supports
- NVIDIA GeForce discrete graphics product family
- https://www.amd.com/en/technologies/rdna.html
Supports
- AMD Radeon RDNA graphics architecture and product family
- https://www.intel.com/content/www/us/en/products/docs/discrete-gpus/arc/arc-graphics.html
Supports
- Intel Arc discrete graphics product family and Xe architecture
- https://developer.apple.com/metal/capabilities/
Supports
- Apple GPU families and Metal feature sets across Apple silicon
- https://www.qualcomm.com/processors/adreno
Supports
- Qualcomm Adreno integrated mobile GPU and sliced architecture
- https://www.arm.com/products/silicon-ip-multimedia?showall=true
Supports
- Arm Mali and Immortalis configurable GPU IP for mobile and embedded systems
- https://www.imaginationtech.com/products/gpu/
Supports
- PowerVR configurable GPU IP for graphics, AI, ray tracing, and power-constrained devices
