Embedded Debugging and Instrumentation
Embedded debugging and instrumentation expose what firmware and hardware are doing inside a target device. Debug probes, breakpoints, trace hardware, and deliberate event records help you inspect failures that ordinary application logs cannot explain.
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Intro
Embedded Debugging and Instrumentation
Embedded debugging is the practice of observing and controlling software on a target device from a separate host computer. Instrumentation adds deliberate measurements or event records to the firmware. Together, they make otherwise hidden processor state, timing, peripheral activity, and failure context available for analysis.
An embedded target often cannot run a full debugger itself. It may have little memory, no display, no filesystem, and strict timing requirements. The common arrangement therefore separates the work across several components:
source + ELF/DWARF symbols
│
▼
host debugger ── remote protocol ── debug server ── USB ── probe
│
JTAG or SWD
│
▼
target debug hardware
│
core, memory, flash, trace sources
The host debugger maps machine addresses back to functions, source lines, and variables by reading the unstripped executable and its debug information. A debug server translates debugger requests into operations understood by the probe. The probe drives the electrical debug transport. On the target, on-chip debug hardware supplies run control, register access, memory access, breakpoints, watchpoints, and optional trace.
Run control and observation
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Sources
- https://documentation-service.arm.com/static/63a03a981d698c4dc521ca77
Supports
- CoreSight debug and trace architecture, component discovery, routing, compliance classes, trace sources, and trace sinks
- Trace pipeline, finite path, filtering, triggering, and capture-limit claims across the intro, slides, cheatsheet, quiz, and infographic source material
- The 2022 timeline event
- https://documentation-service.arm.com/static/5f9009d5f86e16515cdc0417
Supports
- CoreSight architecture history and the 2004 timeline milestone
- https://documentation-service.arm.com/static/6036810d5319e554d4ba108e
Supports
- DWT, ITM, ETM, and TPIU roles and their trace relationships
- Cortex-M run-control and trace claims in the intro, slides, cheatsheet, links, quiz, narration, and 2006 timeline event
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/CoresightWhitepaper.pdf
Supports
- Run-control disturbance, multicore and power-domain concerns, SWD pin reduction, CoreSight DAP, trace routing, and trace bandwidth decisions
- https://documentation-service.arm.com/static/628bad10e3c4322a76af60ef
Supports
- Debug host, client, link, target, and DAP terminology
- Production debug authentication and access-control claims
- Quiz question 10
- https://arm-software.github.io/CMSIS_5/DAP/html/index.html
Supports
- CMSIS-DAP host, USB, JTAG, SWD, and SWO interface model
- CMSIS-DAP reference-link rationale and the 2012 timeline event
- https://arm-software.github.io/CMSIS-DAP/latest/index.html
Supports
- Current CMSIS-DAP probe firmware purpose and high-speed SWO transport direction
- CMSIS-DAP reference-link rationale
- https://arm-software.github.io/CMSIS_5/DAP/html/dap_revisionHistory.html
Supports
- CMSIS-DAP beta, SWO, multi-drop, and bulk-transfer revision sequence
- The 2012 timeline event
- https://newsroom.arm.com/news/the-future-of-debug-and-trace-has-arrived
Supports
- CoreSight SoC-600 introduction and the 2016 timeline event
- https://openocd.org/doc/html/About.html
Supports
- Debug adapter, electrical transport, target, GDB server, flash, and boundary-scan arrangement
- Intro, slides, cheatsheet, practice, quiz question 1, reference rationale, narration, and the 2005 timeline event
- https://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
Supports
- JTAG and SWD selection, topology, pin-count distinction, boundary scan, and flash-programming relationships
- Practice commands and quiz question 5
- https://openocd.org/doc/html/GDB-and-OpenOCD.html
Supports
- GDB connection, target programming, monitor commands, breakpoint behavior, and server workflow
- Practice-reference commands and reference-link rationale
- https://openocd.org/doc/html/General-Commands.html
Supports
- Reset, halt, resume, adapter speed, and target-control command context
- https://openocd.org/pages/documentation.html
Supports
- OpenOCD thesis origin, project documentation, and the 2005 timeline event
- https://www.sourceware.org/gdb/current/onlinedocs/gdb
Supports
- Source-level debugger, registers, memory, stack, breakpoints, watchpoints, remote target, logging, dump, and examine-memory behavior
- GDB commands throughout the cheatsheet and practice reference
- https://www.sourceware.org/gdb/current/onlinedocs/gdb.html/Connecting.html
Supports
- Remote versus extended-remote sessions and exact matching host executables and target libraries
- Matching ELF claims, quiz questions 2 and 8, reference rationale, and practice commands
- https://www.sourceware.org/gdb/current/onlinedocs/gdb.html/Files.html
Supports
- Symbol files, target libraries, sysroot behavior, and the need for matching target files
- Post-mortem symbolication claims and quiz questions 8 and 9
- https://sourceware.org/gdb/current/onlinedocs/gdb.html/Set-Watchpoints.html
Supports
- Hardware and software watchpoint behavior and limitations
- Quiz question 3 and watchpoint guidance
- https://www.gnu.org/software/gdb/
Supports
- Current GNU Project debugger identity and the 1986 timeline event
- https://en.wikipedia.org/wiki/GNU_Debugger
Supports
- The documented 1986 first implementation date used in the timeline
- https://grouper.ieee.org/groups/1149/1/
Supports
- IEEE 1149.1 Test Access Port, boundary-scan scope, observation, and modification functions
- JTAG claims and the 1990 timeline event
- https://standards.ieee.org/standard/1149_1-1990.html
Supports
- Publication identity of IEEE 1149.1-1990 for the timeline
- https://www.eetimes.com/group-offers-debug-standard-for-multi-processor-embedded-systems/
Supports
- IEEE-ISTO 5001-1999 publication and its unified embedded debug interface purpose
- The 1999 timeline event
- https://docs.riscv.org/reference/debug/introduction.html
Supports
- RISC-V halt, resume, register, memory, system-bus, and version-history model
- Architecture breadth in the intro and links plus the 2018 timeline event
- https://riscv.org/wp-content/uploads/2019/06/10.05-TechCommitteeUpdate-June-2019-Copy.pdf
Supports
- Ratification date for RISC-V Debug Specification 0.13.2 used in the timeline
- https://docs.zephyrproject.org/latest/services/tracing/index.html
Supports
- RTOS event tracing concepts, formats, and transport backends
- Zephyr reference-link rationale
- https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/
Supports
- RTT memory-buffered debug transfer role and instrumentation-channel comparison
- https://interrupt.memfault.com/blog/cortex-m-hardfault-debug
Supports
- Cortex-M fault registers, stacked context, post-mortem analysis, and matching build practices
- Awesome-link rationale and quiz question 9
- https://github.com/sindresorhus/awesome
Supports
- Discovery path to the Awesome Electronics list
- https://github.com/kitspace/awesome-electronics
Supports
- Discovery of WaveDrom and the Awesome Embedded Systems list
- https://github.com/embedded-boston/awesome-embedded-systems
Supports
- Discovery of PlatformIO and the Interrupt embedded-systems publication
- https://docs.platformio.org/en/latest/plus/debugging/index.html
Supports
- PlatformIO probe, target, debug server, and project debugging configuration
- PlatformIO awesome-link rationale
- https://wavedrom.com/tutorial.html
Supports
- WaveDrom timing and signal-diagram capability
- WaveDrom awesome-link rationale
- https://openocd.org/
Supports
- OpenOCD landscape entry
- https://pyocd.io/
Supports
- pyOCD CMSIS-DAP, Arm Cortex-M, GDB server, flash, and RTOS-aware landscape placement
- https://probe.rs/
Supports
- probe-rs Arm and RISC-V probe, flash, debug, and target-output landscape placement
- https://www.segger.com/products/debug-probes/j-link/
Supports
- J-Link probe, JTAG, SWD, RTT, and trace landscape placement
- https://www.st.com/en/development-tools/st-link-v3set.html
Supports
- ST-LINK STM32, JTAG, SWD, programming, and Serial Wire Viewer landscape placement
- https://www.lauterbach.com/products/trace32
Supports
- TRACE32 multicore, heterogeneous, run-control, RTOS, and trace landscape placement
- https://www.pemicro.com/products/product_viewDetails.cfm?product_id=15320168
Supports
- Multilink architecture support, programming, and debug probe landscape placement
- https://www.keil.arm.com/mdk-community/
Supports
- Keil MDK Cortex, CMSIS, debugger, and community licensing landscape placement
- https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm
Supports
- IAR Embedded Workbench compiler, C-SPY debugger, Arm target, and analysis landscape placement
- https://www.segger.com/products/development-tools/systemview/
Supports
- SystemView task, interrupt, CPU-load, event, RTT, and free-tool landscape placement
- https://percepio.com/tracealyzer/
Supports
- Tracealyzer RTOS scheduling, interrupt, user-event, interval, state, live, and snapshot trace placement
- https://memfault.com/
Supports
- Memfault fleet fault, log, metric, and post-mortem landscape placement
