CPU Architecture

CPU architecture covers the internal design of processors: instruction pipelines, execution units, branch predictors, caches, and the microarchitectural features that determine how fast instructions complete. It explains why the same code runs at different speeds on different chips.

itComputer architecture and hardware

Don't Panic: CPU Architecture

A CPU turns machine instructions into observable work. It sounds like a job description written on a very small business card, but it is enough to start. A program supplies instructions. The CPU fetches one, decodes it, finds operands, performs the operation, records the result, and chooses where to look next. Without that path, software is a detailed list with nobody moving down it.

The durable distinction is between an instruction set architecture, or ISA, and a microarchitecture. The ISA is the contract visible to software: instructions, registers, memory behavior, exceptions, and privilege rules. A microarchitecture is the machinery chosen to keep that contract. Two processors can run the same machine code while having different pipelines, caches, predictors, timing, and energy use. Compatibility does not mean identical manners.

Modern CPUs overlap the instruction path. While one instruction executes, another may decode and another may be fetched. That is a pipeline, and it improves throughput when the work cooperates. Unfortunately, work has a habit of being related to other work. A result may not exist yet, a branch may not reveal the next address, or two operations may want one resource. The CPU then stalls, forwards a result, predicts, or finds independent work. None of these is magic. They are ways to keep useful work ready while the inconvenient part catches up.

The surprising fact is that a CPU can be busy without making the program finish quickly. A wide execution engine cannot rescue a chain of dependencies. A fast clock cannot make main memory answer sooner. More cores cannot split a serial task into polite pieces because a brochure has introduced them. Ask where useful work waits: the front end, an execution resource, a branch redirect, a cache or TLB miss, memory traffic, or the lack of independent work.

Memory deserves its own quiet alarm bell. Registers and caches are close to execution, while main memory is farther away. Locality means reusing nearby or recent data so the hierarchy can help. Virtual addresses add a translation path, and the TLB caches recent translations. Data-layout changes can therefore alter elapsed time even when the algorithm's mathematical result is unchanged. The machine has not become offended. It has merely had to wait somewhere else.

Read the intro for the contract, pipeline, memory, and privilege model. Use the slides when relationships matter more than detail, and keep the cheatsheet nearby for hazards, cache events, translations, and multicore terms. The reference links lead from a small processor model to real ISA manuals. The exercise then gives the waiting question a stopwatch, which is less glamorous than a clock-frequency argument and considerably more useful.

Don't Panic: CPU Architecture

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