CPU Architecture
CPU architecture covers the internal design of processors: instruction pipelines, execution units, branch predictors, caches, and the microarchitectural features that determine how fast instructions complete. It explains why the same code runs at different speeds on different chips.
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Intro
CPU Architecture
A central processing unit, or CPU, executes the machine instructions that make software run. CPU architecture gives you a working model of that process. It connects an instruction set, a processor core, memory, and the operating system.
You do not need to design silicon to use this model. It helps you read performance data, understand assembly, choose hardware, and explain why two compatible processors behave differently.
Architecture is a contract
An instruction set architecture, or ISA, defines the behavior software can observe. It specifies instructions, registers, data types, control flow, memory behavior, and events such as exceptions.
A microarchitecture is a particular implementation of an ISA. It defines internal choices such as pipeline depth, execution units, cache organization, and instruction timing.
The distinction is practical:
- The ISA says what a correct instruction does.
- The microarchitecture decides how to perform that instruction.
Two processors can run the same machine code while using different internal designs. Arm documents Cortex-A53 and Cortex-A72 as different microarchitectures implementing the same architecture. RISC-V also separates its software-visible ISA from implementation details.
Follow one instruction
A simple processor appears to repeat a short cycle:
- Fetch an instruction from the address in the program counter.
- Decode the instruction into an operation and operands.
- Read source registers or request data from memory.
- Execute the operation.
- Write the result.
- Select the next instruction address.
This sequence explains the dependencies. It is not a literal schedule for every CPU. Modern cores overlap these steps across many instructions.
The program counter identifies an instruction address. A sequential instruction advances it. A branch, jump, call, return, exception, or interrupt can choose another address.
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Sources
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Introducing%20the%20Arm%20architecture.pdf?revision=0b6b67ea-edd7-4975-b23c-d4904ac0cb35
Supports
- Architecture as the software-visible functional specification
- Microarchitecture as implementation details including pipelines, caches, and timing
- Different microarchitectures implementing one compatible architecture
- In-order and out-of-order implementation examples
- https://docs.riscv.org/reference/home/index.html
Supports
- Current ratified unprivileged and privileged RISC-V specification sets
- Base instruction sets, extensions, profiles, and privileged architecture as separate specification areas
- https://docs.riscv.org/reference/isa/unpriv/intro.html
Supports
- ISA as a software-visible interface independent of a particular microarchitecture
- Separation of unprivileged instructions from privileged architecture
- Instruction-set extensions and implementation flexibility
- https://docs.riscv.org/reference/isa/unpriv/rv32.html
Supports
- General-purpose registers and program-counter state
- Register operands, instruction encodings, and control-flow changes
- https://docs.riscv.org/reference/isa/unpriv/rvwmo.html
Supports
- Memory consistency as rules for values returned by loads
- Cross-hart observations under RVWMO
- Explicit synchronization through fences and atomic instructions
- Distinction between a memory model and a required cache implementation
- https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
Supports
- Intel architecture and programming environment
- Basic architecture and instruction-reference organization
- Memory management, protection, interrupts, exceptions, and multiprocessor support
- Optimization documentation for processor implementation behavior
- https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/hardware-behavior-related-to-speculative-execution.html
Supports
- Control-flow and data prediction
- Speculative execution before assumptions resolve
- Retirement of correct work and squashing of mispredicted work
- Transient execution effects and security implications
- https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/refined-speculative-execution-terminology.html
Supports
- Out-of-order execution and speculative use of predicted values
- Architectural and microarchitectural effects of transient instructions
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/LearnTheArchitecture-MemoryManagement-101811_0100_00_en.pdf?revision=1fdc3375-d81c-4457-b786-04fb98557de0
Supports
- Virtual-to-physical address translation through translation tables
- TLBs as caches of interpreted translations
- Address-space permissions and translation faults
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c9/c9s1/
Supports
- Stored-program processor organization
- Program counter, instruction fetch, decode, datapath, control, and next-address behavior
- ISA as a functional contract between software and hardware
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c15/c15s1/
Supports
- Pipelining as overlapped instruction execution
- Latency and throughput distinctions
- Data and control hazards, stalls, forwarding, and branch handling
- Workload instruction count, cycles per instruction, and clock period as performance factors
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c14/c14s1/
Supports
- Cache hits, misses, fills, and hierarchy levels
- Temporal and spatial locality
- Working sets and storage latency-capacity tradeoffs
- Separate instruction and data cache roles