Computer Architecture Fundamentals
Computer architecture describes how processors, memory, and I/O systems are organized to execute instructions. It covers instruction sets, pipelining, caches, branch prediction, and the trade-offs hardware designers make between speed, power, and cost.
itComputer architecture and hardware | OpenSkills.info
Intro
Computer Architecture Fundamentals
Computer architecture explains how software-visible operations become work inside a computer. It gives you a map between source code, machine instructions, processors, memory, and devices.
You do not need to design a processor to use this map. It helps you interpret performance results, choose hardware, debug low-level failures, and understand what operating systems and compilers manage for you.
The central contract
An instruction set architecture, or ISA, defines the behavior software can rely on. It describes instructions, registers, data types, memory behavior, and events such as exceptions.
The ISA is a contract between hardware and software. A compiler can target the contract without knowing the exact circuit design. A processor can change internally while continuing to run compatible software.
A microarchitecture is one implementation of an ISA. It includes details such as pipeline layout, cache sizes, and instruction timing. Two processors can implement the same ISA with different performance, cost, and energy use.
Keep this distinction close:
- Architecture says what software observes.
- Microarchitecture says how a processor delivers that behavior.
The stored-program model
Most general-purpose computers follow a stored-program model. Main memory holds instructions and data as binary values. The processor decides how to interpret each value from its current operation and address.
The basic execution loop is:
Continue the course
This section is part of the paid course.
See pricing to subscribe, or log in if you already have access.
Where this skill leads
Relevant careers
See how this topic contributes to broader role-level skill maps.
Sources
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c9/c9s1/
Supports
- Stored-program organization with processor, memory, and input-output devices
- Instructions and data represented in main memory
- Program counter, fetch, decode, datapath, control unit, and next-address behavior
- ISA as the functional contract between hardware and software
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c14/c14s1/
Supports
- Working sets, temporal reuse, and nearby memory access
- Cache hits, misses, fills, and multiple cache levels
- Small fast storage combined with larger slower storage
- Hardware and software roles across memory-hierarchy levels
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Introducing%20the%20Arm%20architecture.pdf
Supports
- Architecture as a functional specification and hardware-software contract
- Microarchitecture as implementation, including pipelines, caches, and timing
- Multiple microarchitectures implementing one compatible architecture
- Architecture coverage of exceptions, memory ordering, and cache behavior
- https://docs.riscv.org/reference/home/index.html
Supports
- Current ratified RISC-V unprivileged and privileged specification sets
- Separation of user-level instructions from execution modes and system control
- https://docs.riscv.org/reference/isa/v20250508/unpriv/intro.html
Supports
- ISA as a software-visible interface independent of a particular microarchitecture
- Base integer ISAs plus optional standard extensions
- Register width, address-space variants, memory behavior, and parallel implementations
- https://docs.riscv.org/reference/isa/unpriv/rv32.html
Supports
- General-purpose register state and program counter
- Architectural use of registers for operands and addresses
- https://docs.riscv.org/reference/isa/priv/priv-intro.html
Supports
- Privilege levels and operating-system support
- Trap handling and transfer between application and handler execution
- Separation between unprivileged ISA and privileged architecture
- https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
Supports
- Production architecture and programming-environment documentation
- Instruction reference structure
- Memory management, protection, interrupts, exceptions, and multiprocessor support
- https://ocw.mit.edu/courses/6-823-computer-system-architecture-fall-2005/
Supports
- Advanced study path through ISA design, pipelines, caches, virtual memory, input-output, and parallel computers
- Workload and implementation factors in computer-system design
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c15/c15s1/
Supports
- Execution time as instruction count times cycles per instruction times clock period
- Pipelining as overlapped instruction execution that improves throughput
- Data and control hazards, stalls, forwarding, and branch handling
- https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c18/c18s1/
Supports
- Device polling compared with event-driven interrupt handling
- Interrupt transfer to operating-system handlers
- Memory-mapped input-output using ordinary load and store instructions
- https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/exploring-how-cache-coherency-accelerates-heterogeneous-compute
Supports
- Cache coherence as consistent visibility of shared data across processors
- Atomic operations as a separate mechanism for synchronization
- Hardware and software approaches to cache coherence
- https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/hardware-behavior-related-to-speculative-execution.html
Supports
- Branch prediction and speculative instruction execution
- Squashing mispredicted work so it does not affect architectural state
- Security limits of an architectural-results-only model
- https://ocw.mit.edu/courses/6-172-performance-engineering-of-software-systems-fall-2018/resources/lecture-4-assembly-language-computer-architecture/
Supports
- Translation path from source code through machine code to hardware execution
- Assembly and architecture as foundations for software performance analysis
- https://www.nand2tetris.org/
Supports
- Official project sequence for building a system from logic through hardware and software layers