Computer Architecture Fundamentals

Computer architecture explains how software-visible operations become work inside a computer. It gives you a map between source code, machine instructions, processors, memory, and devices.

You do not need to design a processor to use this map. It helps you interpret performance results, choose hardware, debug low-level failures, and understand what operating systems and compilers manage for you.

The central contract

An instruction set architecture, or ISA, defines the behavior software can rely on. It describes instructions, registers, data types, memory behavior, and events such as exceptions.

The ISA is a contract between hardware and software. A compiler can target the contract without knowing the exact circuit design. A processor can change internally while continuing to run compatible software.

A microarchitecture is one implementation of an ISA. It includes details such as pipeline layout, cache sizes, and instruction timing. Two processors can implement the same ISA with different performance, cost, and energy use.

Keep this distinction close:

• Architecture says what software observes.
• Microarchitecture says how a processor delivers that behavior.

The stored-program model

Most general-purpose computers follow a stored-program model. Main memory holds instructions and data as binary values. The processor decides how to interpret each value from its current operation and address.

The basic execution loop is:

1. Use the program counter to locate the next instruction.
2. Fetch the instruction from memory.
3. Decode its fields.
4. Read the required operands.
5. Execute the operation.
6. Store a result when the instruction produces one.
7. Update the program counter.

A branch, jump, call, return, exception, or interrupt can change the next instruction address. Otherwise, execution continues to the following instruction.

This loop is a mental model, not a timing diagram. A modern processor can overlap several instructions, predict future control flow, and execute work out of order. It must still preserve the architectural behavior promised to software.

What lives in a processor

The processor combines a datapath with a control unit.

The datapath moves and transforms values. It contains registers, arithmetic and logic units, and paths that connect them. An arithmetic logic unit, or ALU, performs operations such as addition, comparison, and bitwise logic.

The control unit interprets instructions and directs the datapath. It selects operands, chooses an operation, controls memory access, and decides how the program counter changes.

Registers are small storage locations directly available to instructions. They hold operands, addresses, and intermediate results. Accessing a register is different from loading a value from main memory. An ISA specifies the registers software sees, while a microarchitecture may use additional internal storage.

Instructions express limited operations

Machine instructions usually fall into a few functional groups:

• Data movement transfers values between registers and memory.
• Arithmetic and logic transform values.
• Control-flow instructions select the next instruction.
• System instructions request or control privileged behavior.
• Atomic instructions coordinate shared-memory updates.

An instruction encoding divides bits into fields. Fields can identify an operation, source registers, a destination register, or an immediate value stored inside the instruction.

Different ISAs make different choices. RISC-V uses a required base integer ISA plus optional extensions. Intel 64 retains a much larger historical instruction set. Both provide a software-visible contract, but their encodings and capabilities differ.

Memory is a hierarchy

One storage technology cannot provide the lowest latency, largest capacity, and lowest cost at the same time. Computers therefore arrange storage as a hierarchy.

From closest to the processor outward, a common path is:

registers -> caches -> main memory -> persistent storage

The closest levels are smaller and faster. More distant levels are larger and slower. A cache keeps copies of recently used blocks from the next level.

A cache hit finds the requested block in the cache. A cache miss requires access to another level. Caches work because programs often reuse recently accessed data and access nearby addresses. These patterns are called temporal and spatial locality.

The hierarchy changes how long operations take. A program can execute the same instructions on the same ISA yet run at different speeds because its access pattern produces different cache behavior.

Addresses connect software to storage

Software refers to memory by address. In a system with virtual memory, an application uses virtual addresses. The processor and operating system cooperate to translate them to physical addresses.

Virtual memory supports isolation and flexible placement. It does not mean every address is already present in main memory. Translation and movement between storage levels add their own costs.

An address also can select a device register in systems that use memory-mapped input and output. A load or store can then communicate with hardware instead of ordinary memory. The platform defines those address regions and their behavior.

Input, output, and asynchronous events

A useful computer must communicate beyond the processor and main memory. Devices connect through controllers and interconnects. They expose data and control mechanisms that system software manages.

Polling makes a processor repeatedly check device state. An interrupt lets a device or timer request attention asynchronously. The processor suspends normal execution at an architectural boundary, records enough state, and transfers control to a handler.

An exception is also a transfer to a handler, but it is associated with instruction execution. Examples include an unsupported instruction or a memory access fault. Architecture manuals often group interrupts and exceptions under a broader trap mechanism.

Parallel work changes the rules

A core is a processing unit that can execute an instruction stream. A processor can contain several cores. A core can also expose more than one hardware thread.

Multiple instruction streams can improve throughput, but shared data creates coordination problems. Caches may hold copies of the same memory block. A cache-coherence mechanism keeps those copies consistent according to defined rules. A memory model defines which orderings of memory operations software may observe.

Parallel code needs synchronization even on coherent hardware. Coherence does not make a multi-step update atomic, and it does not impose every ordering a program might assume.

Performance is more than clock rate

Execution time depends on the amount of work and the time required for that work. Clock frequency describes cycles per second. It does not describe how many instructions complete per cycle or how much useful work each instruction performs.

A practical investigation separates several factors:

• Instruction count from the program and compiler
• Cycles required per instruction on the workload
• Clock period of the processor
• Cache and memory stalls
• Branch prediction and pipeline effects
• Available parallelism
• Input and output delays

Compare systems with a representative workload and measured elapsed time. A single architecture label, core count, or frequency cannot predict application performance by itself.

Where this knowledge helps

Use architecture fundamentals when you:

• Read assembly generated by a compiler
• Explain why data layout affects performance
• Interpret cache, branch, and instruction counters
• Choose between latency, throughput, energy, and cost goals
• Debug faults at the boundary between software and hardware
• Evaluate whether parallel work will benefit from more cores
• Read an ISA or platform manual without confusing guarantees with implementation details

This course gives you the map. Deeper competence comes from studying a concrete ISA, tracing a simple datapath, measuring real programs, and then exploring caches, virtual memory, pipelines, and multicore systems separately.

Limits of the model

The fetch-decode-execute sequence hides overlap and speculation. The simple memory ladder hides translation caches, prefetchers, nonuniform memory access, and device-specific behavior. The processor-memory-device picture also hides accelerators and complex system-on-chip interconnects.

Use the simple model to locate a question. Then replace the relevant part with the detailed model from the architecture and platform documentation.