Assembly Language Fundamentals
Assembly language is a low-level programming language that maps closely to a processor's machine instructions. Writing assembly means working directly with registers, memory addresses, and CPU operations, which is necessary for firmware, performance-critical code, and understanding how higher-level languages translate to hardware.
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Don't Panic
Don't Panic - Assembly Language Fundamentals
Assembly Language Fundamentals is the subject of this course. Assembly language gives readable names to machine instructions, registers, and addresses. An assembler translates those statements into machine code for one target architecture.
The useful unit of work is a closed loop: clarify the goal and boundaries, gather the inputs the practice requires, make the decision or change, record evidence, and return with owners for the next cycle. Skipping any link leaves teams busy without durable results.
Tooling supports the loop; it does not replace it. Choose tools after the boundary and evidence model are clear. Comparing products without that model produces feature matrices that do not change how the work runs.
Common failure modes include undefined ownership, metrics that count activity instead of outcomes, and irreversible steps taken without a review path. Treat those as design defects in the practice, not as individual heroics to compensate later.
Operators should be able to explain which signals would change a decision this week. If no signal can change the plan, the practice has become ritual. Keep the feedback path short enough that evidence still influences the next cycle.
Name the owners for each stage of the loop before the work scales. Unowned stages become permanent exceptions. Record decisions with enough context that a future operator can tell why a tradeoff was accepted. Prefer fewer, sharper metrics that change behavior over broad dashboards that only describe activity after the fact.
Read the Intro for the core model. Use the Cheatsheet when you need the operating map. Updates tracks official guidance when this course configures an update source; otherwise the practice is settled without a live feed.
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Sources
- https://sourceware.org/binutils/docs/as/Manual.html
Supports
- GNU assembler documentation covers source syntax, symbols, constants, expressions, directives, invocation, and machine-dependent features
- Architecture manuals, rather than the assembler manual, define architecture instructions, registers, and addressing modes
- https://sourceware.org/binutils/docs/as/Statements.html
Supports
- A statement can begin with labels and then an instruction or directive
- Instruction statements assemble into machine instructions and accepted instructions vary by target
- A label is a symbol followed by a colon in the general GNU assembler syntax
- https://sourceware.org/binutils/docs/as/Symbols.html
Supports
- Symbols name locations or values used in assembly expressions and references
- Symbol values associated with relocatable sections can change during linking
- https://sourceware.org/binutils/docs/as/Pseudo-Ops.html
Supports
- Assembler directives control object construction, data, sections, alignment, symbols, and metadata
- GNU assembler directive names generally begin with a period
- https://sourceware.org/binutils/docs/as/i386_002dSyntax.html
Supports
- GNU assembler supports AT&T and Intel syntax for x86
- The two syntaxes differ in operand notation and ordering conventions
- https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
Supports
- Intel Volume 1 defines the Intel 64 and IA-32 architecture and programming environment
- Intel Volumes 2A through 2D define instruction formats and provide instruction reference pages
- Architecture documentation is required to interpret target-specific registers, modes, widths, instructions, and encodings
- https://developer.arm.com/documentation/102374/latest/
Supports
- A64 instructions operate on architecture-defined general-purpose, floating-point, and vector registers
- The guide covers memory access, data processing, branches, calls, and A64 instruction syntax
- Register names and selected register views determine operation width in documented A64 forms
- https://github.com/riscv/riscv-isa-manual
Supports
- The RISC-V instruction-set manual is organized into unprivileged, privileged, and profile volumes
- Ratification status is identified by the specification volumes, with official versions and current drafts published separately
- ISA specifications define architecture-specific instruction behavior rather than a universal assembly language
- https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst
Supports
- A procedure-call standard lets separately written, compiled, and assembled routines interoperate
- The contract defines caller and callee obligations, register roles, argument and result passing, and stack constraints
- Caller-saved and callee-saved register categories come from an ABI procedure-call standard
- https://refspecs.linuxfoundation.org/elf/gabi4%2B/ch4.symtab.html
Supports
- An ELF symbol table contains information used to locate and relocate symbolic definitions and references
- Undefined symbols can identify references resolved from another object during linking
- https://refspecs.linuxfoundation.org/elf/gabi4%2B/ch4.reloc.html
Supports
- Relocation records identify places and rules for adjusting address-dependent object contents
- Relocation connects symbolic references with final placement during linking
- https://refspecs.linuxfoundation.org/elf/gabi4%2B/ch5.intro.html
Supports
- Executable and shared object files are used to create a running process image
- Program loading maps file segments into memory and dynamic linking completes symbolic references among loaded objects
- https://sourceware.org/binutils/docs/ld/Overview.html
Supports
- GNU ld combines object and archive files, relocates their data, and resolves symbol references
- Linker scripts control input-section mapping and output-file memory layout
- https://sourceware.org/binutils/docs/binutils/objdump.html
Supports
- GNU objdump displays object-file headers, sections, symbols, relocations, raw contents, and disassembly
- The disassemble option decodes sections expected to contain instructions
- Source and raw instruction bytes can be shown with documented options when supporting data is available
- https://sourceware.org/gdb/current/onlinedocs/gdb.html/Machine-Code.html
Supports
- GDB disassembles address ranges and can display raw instruction bytes with symbolic instructions
- GDB maps source lines and machine-code addresses when debug information is available
- GDB can select Intel or AT&T disassembly flavor for x86
- https://www.sourceware.org/gdb/current/onlinedocs/gdb.html/Registers.html
Supports
- GDB exposes program-counter and stack-pointer register aliases where supported and lists target registers
- ABI knowledge determines caller-saved and callee-saved register interpretation across frames
- https://sourceware.org/gdb/current/onlinedocs/gdb.html/Continuing-and-Stepping.html
Supports
- GDB can execute and stop after one machine instruction
- Instruction stepping differs from source-line stepping
- https://sourceware.org/gdb/current/onlinedocs/gdb.html/Optimized-Code.html
Supports
- Optimized machine code can make variables, source order, and source-level stepping differ from an unoptimized build
- Compiler transformations limit one-to-one mapping between source statements and machine instructions
- https://sourceware.org/gdb/current/onlinedocs/gdb.html/Inline-Functions.html
Supports
- Optimization can inline a function body at its call site
- Inlining changes the machine-level call structure visible during instruction stepping
