ARM Architecture
ARM architecture is a family of reduced instruction set computing (RISC) processor designs used in most smartphones, tablets, embedded systems, and an increasing share of servers and laptops. Its power-efficient design trades instruction complexity for lower energy consumption per operation.
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Intro
ARM Architecture
The Arm architecture is a functional contract between software and a processing element. It defines the behavior that software can depend on. That contract covers instructions, registers, exceptions, memory behavior, and debug facilities.
The contract is not a processor design. Two processors can implement the same Arm architecture while using different pipelines, cache sizes, and execution strategies. Their conforming software sees the same architectural behavior, but their performance and power use can differ.
This distinction gives you the first useful mental model:
software
│ depends on
▼
Arm architecture ── implemented by ──> processor microarchitecture
│ │
│ common contract │ concrete design
▼ ▼
instructions, registers, pipelines, caches,
exceptions, memory rules timing, prediction
Use the architecture when you need to know what software may assume. Use a processor technical reference manual when you need implementation details. Use the system-on-chip documentation when you need the memory map, peripherals, or board-specific behavior.
Start with the three profiles
Arm divides its processor architecture into three profiles. Each profile targets a different class of system.
| Profile | Primary design target | Typical software environment |
|---|---|---|
| A-profile | Application systems and high performance | Complex operating systems, applications, and virtualization |
| R-profile | Real-time systems | Timing-sensitive embedded control and safety-oriented workloads |
| M-profile | Microcontrollers | Small, power-constrained embedded systems |
The profiles share architectural ideas, but they are not interchangeable labels. An A-profile operating-system kernel expects facilities that differ from an M-profile firmware environment. Identify the profile before reading register names, exception rules, or memory-management details.
Do not confuse a profile with a product family. Cortex is a brand for Arm processor implementations. Other vendors can also implement the Arm architecture. A processor name tells you which implementation you have. An architecture name tells you which contract it implements.
Decode architecture names
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Sources
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Introducing%20the%20Arm%20architecture.pdf?revision=0b6b67ea-edd7-4975-b23c-d4904ac0cb35
Supports
- Architecture as a functional contract between hardware and software
- A-profile, R-profile, and M-profile targets
- Architecture versus microarchitecture
- Architecture naming, implementation-defined features, and documentation layers
- Cortex as processor IP rather than the complete Arm architecture
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20Instruction%20Set%20Architecture.pdf?revision=ebf53406-04fd-4c67-a485-1b329febfb3e
Supports
- A64 as the instruction set for AArch64 and its fixed 32-bit instruction width
- A32 and T32 as instruction sets for AArch32
- Simple sequential execution and permitted internal microarchitectural optimization
- AArch64 general-purpose, floating-point, vector, and system register concepts
- Instruction-definition fields and interaction with compiled code
- https://developer.arm.com/documentation/102374/latest/
Supports
- Thirty-one AArch64 general-purpose registers
- X and W register views and zeroing of upper bits after a W-register write
- A64 instruction classes, loads and stores, branches, and system operations
- Maintained study path for the AArch64 programmer's model
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Exception%20model.pdf?revision=a62f2bf2-b08a-4a4f-8cbe-38c67ddf4434
Supports
- Exception levels and conventional application, kernel, hypervisor, and firmware roles
- Required EL0 and EL1 and optional EL2 and EL3 in Armv8-A
- AArch64 and AArch32 execution states
- Synchronous and asynchronous exceptions
- Exception entry, saved return state, vectors, and exception return
- System-register access associated with Exception levels
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20memory%20model%20guide.pdf?revision=58b1dd0a-3800-4218-b21a-f95a0332034c
Supports
- Normal and Device memory types
- Translation-table descriptors and access attributes
- Permissions, execute controls, cacheability, and shareability
- Memory-access ordering as distinct from instruction execution order
- Low-level relevance to boot code, drivers, and MMU management
- https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/LearnTheArchitecture-MemoryManagement-101811_0100_00_en.pdf?revision=1fdc3375-d81c-4457-b786-04fb98557de0
Supports
- Virtual-address translation and translation-table structure
- Stage 1 virtual-to-intermediate translation
- Stage 2 intermediate-to-physical translation under a hypervisor
- AArch64 address-space configuration and translation faults
- https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst
Supports
- Procedure Call Standard scope for the Arm 64-bit ABI
- Register roles, stack rules, parameter passing, and result return
- Caller-saved and callee-saved register duties
- Distinction between ISA behavior and binary interoperability rules
- https://developer.arm.com/documentation/ddi0602/latest/
Supports
- Searchable normative A64 instruction descriptions
- Encodings, operands, feature conditions, exceptions, and architectural pseudocode
- https://developer.arm.com/documentation/ddi0487/latest/
Supports
- Normative A-profile architecture reference
- Instructions, registers, exceptions, virtual memory, memory ordering, and debug architecture
- Mandatory and optional architectural feature rules
